questions? contact us: marketing@amkor.com visit amkor technology online for locations and to view the most current product information. wafer level processing & die processing services (wlp/dps) amkor offers wafer level chip scale packaging (WLCSP) providing a solder interconnection directly between a device and the motherboard of the end product. WLCSP includes wafer bumping (with or without pad layer redistribution or rdl), wafer level final test, device singulation and packing in tape & reel to support a full turnkey solution. amkors robust under bump metallurgy (ubm) over pbo or pi dielectric layers on the die active surface providing a reliable interconnect solution able to survive harsh board level conditions meeting the demands of the growing global consumer market place for portable electronics. fueling growth ? small packages in mobile are critical to maximize battery size ? level of adoption in fastest growing markets (i.e., tablets and smartphones) ? dis-integration of high performance functions from processors to new specialized devices(e.g., audio) ? fewer cycles through electrical test ? lower cost to ems assembly msl l1 package from t&r ? improved smt-compatible underfill processes at ems companies increase prior die size limits the csp nl bump on repassivation (bor) option provides a reliable, cost- effective, true chip size package on devices not requiring redistribution. the bor option utilizes a repassivation polymer layer with excellent electrical/ mechanical properties. a ubm is added, and solder bumps are then placed directly over die i/o pads. cspnl is designed to utilize industry-standard surface mount assembly and reflow techniques. ds720h rev date: 1/16 WLCSP the csp nl bump on redistribution option adds a plated copper redistribution layer (rdl) to route i/o pads to jedec/eiaj standard pitches, avoiding the need to redesign legacy parts for csp applications. a nickel- based or thick copper ubm offerings, along with polyimide or pbo dielectrics, provide best in class board level reliability performance. cspnl with rdl utilizes industry-standard surface mount assembly and reflow techniques, and does not require underfill on qualified device size and i/o layouts. the csp n3 option utilizes one layer of copper for both redistribution and ubm. this simplified process flow reduces cost and cycle time by over 20%. cspn3 has been in production since 2009 and as of 2015 has a run rate of over 2.8 billion units since its introduction. applications the WLCSP package family is applicable for a wide range of semiconductor device types from high end rf wlan combo chips, to fpgas, power management, flash/eeprom, integrated passive networks and standard analog. WLCSP offers the lowest total cost of ownership enabling higher semiconductor content while leveraging the smallest form factor and one of the highest performing, most reliable, semiconductor package platforms on the market today. WLCSP is ideally suited for, but not limited to, mobile phones, tablets, netbook pcs, disk drives, digital still & video cameras, navigation devices, game controllers, other portable/remote products and some automotive end applications. wafer level features ? 4-196 ball count ? small body 0.64 mm 2 to large 50.0 mm 2 body size ? pbo & polyimide (pi) repassivation and redistribution layer (rdl) available ? electroplated sn/ag < 0.3 m and sac alloy ball-loaded bumping options ?0.3?m ? pitch ? reliable thick cu ubm or ni/au for best in class em performance ? compatible with conventional smt assembly and test techniques die level features ? best in class component and board level reliability ? jedec tested board level performance demonstrated without underfill ? precision edge quality ensuring device integrity at board mount ? back-side laminate coating available ? cost effective t&r packaging solutions for small ics ? ultra-thin backgrinding for embedded die applications ? full turnkey wlp, contact probe and dps supported in taiwan, china and korea ? wide selection of pocket tape carrier options wafer level packaging data sheet
questions? contact us: marketing@amkor.com visit amkor technology online for locations and to view the most current product information. ds720h rev date: 1/16 package options ball loading pitch sphere diameter 0.50 mm 0.30 mm 0.40 mm 0.25 mm 0.30 mm 0.20 mm reliability qualification package level: ? preconditioning at level 1 85c/85% rh, 168 hours, (unlimited out of bag life) reflow @ 260c peak ? temp cycle -55c/+125c, 1000 cycles ? high temp storage 150c, 1000 hours board level: ? temp ? cycle? -40c/+125c,? 15? min.? ramp? rate,? ? 500? cycles ? drop? test ? jedec? condition? b? (1500g),? ?100 ? drops wlpt est dps ? design services available ? layout ? mask tooling ? wa fer rdl patterning and bumping (ball sphere loaded or plated ) ? automated optical inspection (aoi) for best in class quality assurance ? wa fer map generation ? te st software and hardwar e development ? probe card design, service and suppor t ? te st program transfer ? wa fer sort for rf , memory , logic and analog applications ? best in class singulated device edge quality for all si nodes ? shipping material design and supply management ? drop ship to final customer available contact probe inspect & clean pbo or pi 1 rdl seed deposition resist processing cu rdl plating resist & seed removal pbo or pi 2 ubm seed deposition resist processing cu or ni-based ubm resist & seed removal ball place backgrind backside lamination laser mark singulation ta pe & reel aoi process highlights ? die thickness 150 m* to 450 m ? bump height 0.5 mm pitch: 250 m 0.4 mm pitch: 210 m 0.3 mm pitch: 170 m ? solder ball pitch (ball loaded) 0.28, 0.3, 0.35, 0.4, 0.5 mm pitch (plated) 0.12 to 0.25 mm ? solder sphere diameter 0.2, 0.25, 0.3 mm ? redistribution trace/space (min) cspnl: 12/12 m cspn3: 15/15 m ? via diameter (min) pbo: 15 m polyimide: 25 m ? backside laminate (black) available ? saw street (min) 65 m (passivation free space) standard materials ? dielectric materials pbo and polyimide, cure polymers, low cure polymers ? rdl metalization plated copper ? ubm thick cu or ni-based ? solder composition (ball loaded) pb-free sac alloys (plated) sn/ag pb-free, cu pillar shipping carrier t ape 7 , 13 reels *advanced manufacturing rules may be required. contact amkor business unit for additional information. capabilities and services WLCSP wafer level packaging data sheet with respect to the information in this document, amkor makes no guarantee or warranty of its accuracy or that the use of such information will not infringe upon the intellectual rights of third parties. amkor shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon it and no patent or other license is implied hereby. this document does not in any way extend or modify amkors warranty on any product beyond that set forth in its standard terms and conditions of sale. amkor reserves the right to make changes in its product and specifications at any time and without notice. the amkor name and logo are registered trademarks of amkor technology, inc. all other trademarks mentioned are property of their respective companies. ? 2016, amkor technology incorporated. all rights reserved.
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